In recent years, as electronic equipment has become more compact and its level of functionality has increased, chip-on-chip (CoC) type semiconductor devices have been developed, these being provided with a chip stack in which a plurality of semiconductor chips are stacked on one another (see Japanese Patent Kokai 2010-161102 (referred to hereinafter as patent literature article 1)). Each of the semiconductor chips forming the chip stack has through-electrodes which penetrate through a semiconductor substrate. The semiconductor chips are electrically connected to each other by way of the through-electrodes.
In the semiconductor device described in patent literature article 1, one of the semiconductor chips forming the chip stack is a logic chip (an interface chip), and the other semiconductor chips are memory chips. The memory chips have a circuit-forming surface on which memory circuits are formed, and through-electrodes which penetrate through the memory chip. The interface (IF) chip has a circuit-forming surface on which IF circuits are formed, and through-electrodes which penetrate through the IF chip. The logic chip is mounted on a package substrate, and the memory chips are provided on the logic chip.
A plurality of metal balls, forming external terminals, are provided on the package substrate. The arrangement of the metal balls, and the pitch between the metal balls, is generally determined in accordance with standardized specifications. Electrode pads are provided on the surface of the package substrate on the opposite side to the surface on which the external terminals are formed. The electrode pads are electrically connected to electrode pads formed on the IF chip.
The circuit pattern on an IF chip is generally simpler than the circuit pattern on a memory chip, and therefore the surface area of the circuits on the IF chip can be reduced compared with the surface area of the circuits on the memory chip. IF chips are therefore generally smaller than memory chips.
FIG. 1 and FIG. 2 were prepared by the applicant of this application in order to describe one of the problems to be resolved by the invention, and they illustrate an example of the wiring line patterns on the obverse surface and the reverse surface of a package substrate.
FIG. 1 illustrates a wiring line pattern 122 formed on a surface (referred to hereinafter as the reverse surface) of a package substrate 103 on which external terminals 104 are formed. It should be noted that in FIG. 1, for convenience, lines are also included to indicate the external form of an IF chip 101, a core chip 102 and electrode pads 109 formed on the surface (referred to hereinafter as the obverse surface) of the package substrate 103 on the side opposite to the reverse surface thereof. Vias 118a and 118b penetrating through the package substrate 103 are provided in the vicinity of each external terminal 104.
FIG. 2 illustrates a wiring line pattern 123 formed on the obverse surface of the package substrate 103. It should be noted that in FIG. 2, for convenience, lines are also included to indicate the external form of the IF chip 101 and the core chip 102. The vias 118a and 118b, which are electrically connected to the external terminals 104, are connected by way of the wiring lines 123 to the electrode pads 109 formed on the obverse surface of the package substrate 103.
The positions of the external terminals 104 on the package substrate 103 are defined by a standard. The IF chip 101 is smaller than the core chip 102. The electrode pads 109 connect to the electrode pads on the IF chip 101, and are thus arranged in the vicinity of the center of the package substrate 103. The plurality of electrode pads 109 on the package substrate 103 are aligned in one direction in the region in which the IF chip 101 is present. As a result, if the length of the IF chip 101 in the pad row direction (the Y-direction in the drawing) is short, then the density of the wiring lines 123 formed on the obverse surface of the package substrate 103, in other words wiring lines which electrically connect the external terminals 104 to the IF chip 101, is high.
In particular, as illustrated in FIG. 2, the plurality of wiring lines 123 routed from the vias 118a that are electrically connected to the external terminals 104 provided toward the outside of the package substrate 103 become congested. In some cases there may even be vias 118b from which it is difficult to connect a wiring line to a pad 109 formed on the obverse surface of the package substrate 103.
A semiconductor device provided with a package substrate with which wiring lines can be routed easily is therefore desirable.